Trace Table Based Approach forPipelined Microprocessor Veri cationJun Sawada

This paper presents several techniques for formally verifying pipelined microprocessor implementations that contain out-of-order execution and dynamic resolution of data-dependent hazards. Our principal technique models the trace of executed instructions using a table-based representation called a MAETT. We express invariant properties of pipelined implementations by specifying relations between elds in the MAETT. To show the viability of this technique, we have proved the correctness of a simple out-of-order completion pipelined microprocessor design using the ACL2 theorem prover. This veriication was performed incrementally by proving that the speciied relations hold for all micro-architectural states reachable from a ushed implementation state, eventually permitting us to prove that the entire pipelined machine design implements its ISA speciication.